HIGH SPEED INTERFACE 4
August 16, 2005 - wilf rigter
The HS-4 system is a high speed interface between two TS1000 units,
one of which is dedicated to executing a user program in the FAST
mode while the other generates a continuous video display of the
user program DFILE.
The Master TS1000 provides a SLOW mode video display of the application
program running in the FAST mode on the Slave TS1000.
The Slave DFILE is directly transferred to Master DFILE through an
memory mapped HS-4 interface. This is the fastest method short of using
a true DMA chip but the HS-4 is conceptually much simpler to work with.
The HS-4 interface provides the Master TS1000 with Direct Memory Access
to the echo between 48K and 64K of the 16K Slave BASIC MEMORY including
the SYSTEM VARIABLES, PROGRAM and DFILE. If a 64K memory pack is used D6
must be installed which asserts M1 to enable the echo of the 16K to 32K
BASIC RAM page above 32K.
The Master takes control of the SLAVE memory by using BUSRQ with contents
Directly addressed by 16 bit address and SLAVE DFILE data is transferred
directly to the MASTER DFILE using a single LDIR machine code instruction.
HS-4 CONTROL SOFTWARE
The control software that runs on the MASTER TS1000 is a short MC program
The SLAVE System Variable DFILE echo is loaded into HL with the MSB set.
The MASTER System Variable DFILE is loaded into register DE.
The length of a full DFILE is 793d (319h) which is loaded into register BC.
the DFILE is transferred using a single MC instruction LDIR.
LOOP LD HL,(C00C) ; LOAD SLAVE SYSTEM VARIABLE DFILE ECHO INTO HL (SOURCE)
SET bit 7, H ; SET MSB ADDRESS BIT (+32K) TO ACCESS SLAVE DFILE ECHO
LD DE,(400C) ; LOAD MASTER SYSTEM VARIABLE DFILE INTO DE (DESTINATION)
LD BC, 0319h ; LOAD SIZE OF FULL DFILE (931 bytes) INTO BC (LENGTH)
LDIR ; TRANSFER
JR LOOP ; REPEAT
The HS-2 design uses five simple TTL chips.
74HC32 OR gates and 74HC00 NAND gates are used for the MASTER Machine State
Decoder whose state indicates whether the MASTER CPU is running the video
routines or the control program. When generating video, the MASTER only
controls the internal 2K of RAM. When the MASTER is free to run the control
program, the MS decoder automatically takes control of the SLAVE CPU and the
SLAVE BASIC RAM above 32K which is then directly accessible to the MASTER CPU.
The MS decoder decodes the Machine State from the MASTER NMI ON and OFF I/O
commands. The MS Decoder is the same circuit used in the TurboV2 clock-doubler
to decode when the user program is running and the CPU clock can be doubled.
Two 74HC541 octal buffers are used as 16 bit address buffers and are enabled
by both BUSRQ and BUSACK.
A third 74HC541 is used as an 8 bit data buffer is controlled by both the
MASTER RD line and the High Memory decoder circuit that uses A15, MREQ,
and BUSREQ to enable the data buffer. When the MASTER control program is
running and SLAVE data is read above 32K, the data buffer is active and
while the MASTER internal 2K RAMCS line is disabled with D1.
The control hardware and software runs on the Master TS1000. The Master
runs in the SLOW mode and spends most CPU time executing video routines.
When the CPU is free to run the control program, the machine state decoder
asserts the BUSRQ signal on the Slave TS1000 bus. The Slave CPU responds
with BUSACK, which enables the IC3-IC4 the buffers that connect the MASTER
address bus to the Slave memory. The Master then reads the data byte at
at any address above 32K from the SLAVE memory through U5, the data input
port and transfers the byte to the Master memory
The time to transfer one byte using LDIR is about 6.5 us, so a complete
DFILE can take up to 793 x 6.5us = 5ms of CPU time. Since the transfer
will be interrupted during the SLOW video display time, the total time to
transfer DFILE is 1 to 3 frames depending on the vertical frame rate.
The Master Machine State decoder automatically drops the BUSRQ line
during the video display, which allows the SLAVE user program to
In fact, the Slave user program only runs when the Master TS1000 is
generating the video display which means that the Slave user program uses
more than 80% of available Slave CPU time at 60 Hz vertical frame rate.
This means that the FAST TS1000 user program runs 3 times faster than the
normal 50Hz SLOW mode and 5 times faster than the normal 60HZ SLOW mode.
The LDIR instruction increments addresses during the DFILE transfer which
avoids problems if DFILE is not properly formatted (eg after SCROLL).
I like the HS-4 solution the best and I will actually build the HS-4 prototype
first to get baseline information on the performance of this type of interface.
Circuit detailed operation to come